Handling of source synchronous data from a memory device, such as a DRAM, is an important design challenge for a memory interface. The challenge stems from the time variability of a returning strobe signal because of factors such as process, voltage, temperature (PVT), board trace variation and clock uncertainties to name a few. Due to these factors, there can be significant variability between the earliest and latest possible times at which strobe signals start transitioning at an agent interface (i.e., interface between a control chip or controller and the DRAM).
The Double Data Rate (DDR2) protocol stipulates that strobe signals driven by the DRAM have a preamble of one clock cycle. This preamble is defined as the time period preceding the first strobe signal edge when DQS_H (active high strobe signal) is low and DQS_L (active low strobe signal) is high.
In previous memory subsystems developed by the assignee of the present invention (such as for a zx1 chipset), the time variability for the returning strobe signals is less than one clock cycle. This small variability allows a memory controller to generate a core synchronous signal that is guaranteed to be within the preamble of both the earliest and latest possible strobe signals. This core synchronous signal enables internal circuitry of a read data state machine (internal to the core) to begin responding to the input strobe. The result is a core synchronous control scheme that guarantees a deterministic state of the read data state machine.
Through analysis of the memory subsystem in a zx2 chipset developed by the assignee of the present invention, it has been determined that the time variability of read return strobe signals is greater than one clock cycle and that the previously-developed methodology could not be used.